Published: June 2, 2026, 00:57 UTC
For five decades, the logic of semiconductor scaling was simple: shrink the transistor, get more performance, lower power consumption, and reduce cost per transistor. At the 14-angstrom (1.4 nm) and 16-angstrom nodes, that logic is breaking down. The industry faces a paradox summarized in a single phrase from a new analysis by Semiconductor Engineering: “Moore is more, but more is also less.”
The Sub-2nm Paradox, published June 1, is a deep examination of the engineering and economic forces converging on the next generation of chip manufacturing. It draws on interviews with executives from Synopsys, proteanTecs, Lam Research, Intel, and other key players to paint a picture of an industry that can still make transistors smaller — but can no longer do so cheaply, reliably, or uniformly.
The Diminishing Returns Problem
At the 14Å node, the expected performance gain from a full node shrink has fallen to 10–15%, with power reduction in the 20–30% range, according to Abhijeet Chakraborty, VP of Engineering at Synopsys. “The expectation is that because of the shrinking of dimensions you get faster performance, lower power consumption, and higher transistor density,” Chakraborty told Semiconductor Engineering. “The challenge is whether you can attain that promise.”
The gap between promise and reality is driven by fundamental physics. Wires at sub-2nm dimensions are so thin that resistance-capacitance (RC) delay becomes a major bottleneck, eating into the speed gains from smaller transistors. SRAM is “falling way behind scaling for digital logic,” limiting how much cache can fit on a reticle-sized die. Process variation has proliferated wildly — variation can now “creep into hundreds or even thousands of insertion points and dozens of tools,” according to Evelyn Landman, CTO of proteanTecs.
Margin as the Contested Resource
Landman describes margin — the safety buffer engineers build into designs to account for manufacturing imperfections — as “one of the most contested resources at 2nm and 18A.” At sub-2nm nodes, chips must simultaneously handle process variation, thermal effects, workload stress, latent defects, and aging. “Aggregating all of these into a single worst-case guard-band is no longer viable,” she said.
The result is an economic paradox: the most advanced chips now require cutting-edge lithography that only a handful of fabs can operate (Intel Foundry, TSMC, Samsung Foundry, and Japan’s Rapidus), while the yield timelines are stretching longer for each successive node. The cost of a single leading-edge fab has crossed $30 billion, and the number of companies that can afford to design chips at these nodes is shrinking to a handful of hyperscalers and AI companies.
How the Industry Is Adapting
The response is a fundamental shift in how chips are designed and manufactured. Rather than monolithic die shrinks — cramming everything onto one piece of silicon — the industry is moving toward multi-die chiplet assemblies, where smaller, cheaper dies are packaged together. This approach allows designers to use leading-edge logic for the compute cores while using older, cheaper nodes for memory, I/O, and other functions.
Intel is exploring rectangular panel-scale chips measuring 500 × 500 mm — a rectangular extension of the wafer-scale approach that abandons the traditional 300 mm circular wafer entirely. At the same time, design-technology co-optimization (DTCO) has become mandatory: chip designers and process engineers can no longer work independently, because the margin for error at 14Å is measured in atoms.
The material science pipeline is also accelerating. Lam Research’s David Fried notes that “with advanced logic transistor development, we would see a couple of material innovations happen every decade. In my current role — it’s constant.” Tungsten is being replaced by molybdenum; cobalt may give way to ruthenium. Every new material requires new deposition, etching, and cleaning processes — and new opportunities for defects.
The Workload Factor
One of the more surprising findings in the analysis is that AI workloads themselves are reshaping chip design. “Workloads are now first-class design constraints,” Landman said. “Large language model training and inference patterns create highly non-uniform stress across silicon. Temporal bursts, localized hotspots, and long-duration stress patterns can produce very different outcomes on identical silicon.” In short, the same chip running the same code can degrade differently depending on the AI model it serves.
The Sub-2nm Paradox has no easy resolution. The industry will continue to shrink transistors because it has no alternative — AI demand for compute shows no signs of slowing, and the competitive pressure to deliver better performance per watt is relentless. But the era of the free lunch, when a new node delivered automatic gains across every metric, is definitively over.
Sources: Semiconductor Engineering (Ed Sperling, Jun 1, 2026)