Nvidia and Intel both issued high-profile declarations this week about their growing American manufacturing footprints, but the celebrations obscure a stubborn gap: every Blackwell chip fabricated at TSMC’s Phoenix facility still has to cross the Pacific for advanced packaging.
Nvidia’s network of US partners and suppliers now spans 43 states, according to a July 2 blog post by CEO Jensen Huang. TSMC’s Arizona fab is producing Blackwell wafers at volume, Foxconn is building an AI supercomputer assembly plant in Houston, and Wistron is doing the same in Dallas. Nvidia estimates its AI infrastructure investments will contribute US$485 billion (approximately £385 billion) to US GDP in 2026 alone.
But the blog post omits a critical detail confirmed by supply chain analysts: CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging, the process that bonds GPU dies with high-bandwidth memory on a silicon interposer, is performed exclusively in Taiwan. Every Arizona-made wafer must be shipped back to TSMC’s CoWoS lines in Taichung before it becomes a functional Blackwell accelerator.
The Packaging Bottleneck
Advanced packaging has emerged as the binding constraint on AI chip supply, displacing wafer fabrication as the bottleneck. Nvidia has reserved the majority of TSMC’s CoWoS capacity through at least 2027, with that capacity growing at roughly 80% compound annually but still falling short of demand, according to a CNBC report from April.
TSMC is constructing two advanced packaging facilities in Arizona as part of its US$165 billion (approximately £131 billion) US expansion commitment, but those plants sit on a later build schedule than the wafer fabs. In the interim, Amkor Technology, which won Nvidia’s US packaging business for future chips, has yet to achieve production parity with TSMC’s Taiwan lines.
Intel has its own message for the market. The company’s 18A process node has entered risk production with backside power delivery delivering 30% higher frequency, and its foundry business offers EMIB (Embedded Multi-die Interconnect Bridge) and Foveros 3D packaging as alternatives to CoWoS. But Intel’s packaging technology has yet to be qualified for Nvidia’s Blackwell architecture, and the foundry’s broader operational challenges through 2025-2026, including well-documented yield issues, have limited external customer confidence.
The Geographic Concentration Problem
The semiconductor industry’s geographic fragility extends beyond packaging. The US CHIPS Act of 2022 authorized approximately US$52 billion (approximately £41 billion) in grants and tax credits to reshore production, but the funding was heavily weighted toward front-end fabrication. Advanced packaging, a capital-intensive, technically demanding process that TSMC dominates, received far less investment.
Nvidia’s own declared ambitions underscore the gap. The company says it will produce up to US$500 billion (approximately £397 billion) of AI infrastructure in the US with partners including TSMC, Foxconn, Wistron, Corning, Lumentum, Coherent, and Amkor. But as several analysts have pointed out, if every Blackwell chip must be packaged in Taiwan, that number is contingent on a single geographic chokepoint.
“Up to this point, all of TSMC’s advanced packaging capacity is in Taiwan, and that’s where it will remain for at least the next two years,” semiconductor analyst Dan Hutcheson told CNBC in April. “The Arizona packaging fabs are coming, but they are not here yet, and the scaling challenge is enormous.”
Intel Foundry Services has positioned itself as a potential second source for advanced packaging outside Taiwan, offering capacity at its Rio Rancho, New Mexico facility. Yet with Intel’s own financial restructuring underway and customer qualification timelines stretching into 2027, the industry’s packaging dependency on Taiwan is unlikely to shift meaningfully before the end of the decade.
Sources: NVIDIA and Partners Build in America, for America (Nvidia Blog, July 2); Nvidia and Intel tout homegrown American chip supply chain (Tom’s Hardware, July 6); TSMC Advanced Packaging Bottleneck: Why CoWoS Controls AI Chip Supply (Next Waves Insight, April 26); Intel 18A-P enters risk production (Tom’s Hardware, June 2026)