The gap between fast volatile memory and slow persistent storage, known to computer architects as the memory wall, has been a persistent drag on system performance for decades. A team of researchers from the University of Seoul has proposed a way to tear down a section of that wall by integrating DRAM and NAND flash directly at the device level.
The architecture, named NAD memory, combines the density of NAND flash with the speed of DRAM in a single tightly integrated design. The key innovation is removing the intermediary layers (the I/O buffers, data buses, and discrete controllers) that traditionally handle communication between the two memory types. With direct and parallel data paths between DRAM and NAND, the NAD design sharply reduces the latency cost of moving data between the fast and slow tiers of the memory hierarchy.
The paper, published in IEEE Access, describes an architecture that connects DRAM and NAND through cell-level data paths rather than through the traditional bus-based approach. This allows the hybrid memory to function as a single addressable unit, with the system able to read and write across both memory types without the overhead of managing separate protocols and buses.
The practical implications span several domains. In solid-state drives, NAD could reduce the performance penalty of moving data between DRAM buffers and NAND storage arrays. In embedded systems, where the physical footprint of separate memory controllers is a constraint, a unified hybrid chip could save both space and power. For AI and machine learning accelerators, where memory bandwidth is often the limiting factor on throughput, the architecture could alleviate the bottleneck between on-chip memory and external storage.
The research sits within a broader industry trend toward rethinking memory hierarchies for the AI era. Conventional designs that treat DRAM and NAND as separate components connected by a bus were optimized for an earlier generation of workloads. As models grow larger and data sets expand, the cost of moving data between memory tiers is becoming the dominant factor in total system performance.
NAD memory faces the usual challenges of any hybrid architecture: manufacturing complexity, yield rates, and the question of whether the benefits justify the cost of integrating two fundamentally different semiconductor processes on the same die. But as a proof of concept, it points toward a future where the boundary between memory and storage is far less rigid than it is today.
Sources: Semiconductor Engineering (Jul 29, 2026); IEEE Access (vol. 14, pp. 106983–106994, 2026)