Intel Foundry announced that its 18A-P process, the first performance enhancement to the Intel 18A node family, has entered risk production. The milestone, disclosed at the 2026 VLSI Symposium alongside six research papers, marks the company’s most detailed public accounting of how its gate-all-around (GAA) transistors and backside power delivery architecture perform in real designs.
The headline numbers are significant. At 0.5 volts, GAA designs with backside power demonstrated roughly 30% higher frequency compared to FinFET equivalents. Routed blocks showed approximately 11% area reduction from freed frontside interconnect. Dynamic voltage droop measured under 10 millivolts peak on Intel 18A, compared to over 90 millivolts on Intel 3, a tenfold improvement that enables 5-6% frequency uplift or up to 15% power reduction.
Intel 18A-P delivers a 9% performance gain at iso-power or 18% lower power at iso-performance compared to the baseline Intel 18A, measured on a standard ARM core sub-block. The improvement comes from a mix of device options, tighter variation, improved contacts, and design-technology co-optimization.
The process introduces Power Boost, which Intel describes as the industry’s first implementation of a dual contact architecture combining frontside and direct backside contacts, enabled by PowerVia. This improves resistance for both NMOS and PMOS at matched footprint, increasing drive current and frequency.
Thermal resistance improved 20-40% through materials and design innovations. Intel also added a fifth logic threshold voltage pair, giving designers an additional option between ultra-low and low threshold voltages to balance speed and power.
Intel 18A-P is design-rule compatible with 18A, meaning existing 18A designs can adopt the performance gains without full redesign.
Backside Power in Practice
The benefits of backside power delivery extend beyond transistor performance. Lower metal layers no longer need tight spacing, allowing 32-nanometer metal processes with fewer masks and manufacturing steps. This reduces cost and complexity in the interconnect stack.
The <10 millivolt droop figure is particularly important for AI accelerators and high-performance computing, where power integrity at high current loads has become a limiting factor. Voltage margins have been vanishing at advanced nodes as frontside power delivery fails to scale, and backside power directly addresses that bottleneck.
The 11% area reduction from freed frontside interconnect for signal routing translates to more compact designs and better utilization of silicon area.
Beyond 18A: GaN, CFET, and Ruthenium
Intel also presented research on longer-range process technologies. On gallium nitride (GaN), the company demonstrated multi-thousand-gate digital control circuits built on a 300 mm GaN and silicon platform using hybrid GaN nMOS and silicon pMOS. The power-delay product of 6.2 attojoules per stage is over 1,000 times more efficient than prior GaN logic approaches, potentially enabling on-chip control integration that reduces cost and complexity.
On complementary FET (CFET), Intel built working logic circuits at a 45-nanometer gate pitch with a 2×2 ribbon stack, backside power delivery, and direct backside contacts. The work demonstrates a path beyond the current GAA architecture.
On interconnects, Intel presented the first integration of subtractive ruthenium wiring with airgap, demonstrating capacitance reduction up to 35% and via resistance reduction up to 50% compared to copper, with functional RibbonFET devices.
What It Means
Intel’s 18A-P announcement is its strongest signal yet that the company’s foundry turnaround is producing measurable results. The VLSI disclosures include silicon data and routed benchmarks, not just projections. Naga Chandrasekaran, executive vice president and general manager of Intel Foundry, framed it as proof of commitment: “Our updates and presentations at VLSI signal to Intel Foundry customers and partners that we are fully committed to leading edge process innovation over the long term.”
For a company that has missed multiple process milestones in recent years, the 18A-P risk production milestone, supported by detailed performance data, represents a credible step toward rebuilding customer confidence.
Sources: Semiconductor Engineering (June 18, 2026); Intel Community blog (June 16, 2026); Morningstar/Business Wire (June 16, 2026)