IBM has demonstrated a prototype chip that packs approximately 100 billion transistors onto an area the size of a human fingernail, roughly double the density of its previous state-of-the-art announced in 2021. The advance could extend Moore’s Law for another 10 to 15 years, according to industry analysts.
The chip uses a complementary field-effect transistor (CFET) architecture IBM calls “Nanostack”: two layers of transistors stacked vertically on a single piece of silicon. Rather than continuing to shrink transistors horizontally, an approach that has hit fundamental limits due to quantum interference, IBM builds upward.
“It’s not just an incremental step. It’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research.
The process works by fabricating transistors on a bottom silicon layer, placing a second silicon layer on top, building a second set of transistors directly above the first, and creating electrical connections between the layers. A key innovation is that the transistors in the second layer are staggered rather than stacked directly on top of the first, simplifying the wiring between layers. Each transistor channel uses three nanosheets just 15 atoms thick, spaced 9 nanometers apart.
IBM says the design can deliver up to 50 percent more work in the same time, or up to 70 percent greater energy efficiency, depending on the workload.
The company refers to the node as “0.7 nanometer”, a marketing designation rather than a physical dimension, noting that actual transistor spacing remains around 40 nanometers.
“Absolutely, it’s transformational. This puts another ten, fifteen years on the roadmap,” said Dan Hutcheson, vice chair of semiconductor research firm TechInsights.
Other companies including Intel, Samsung, TSMC, and Belgium’s Imec are also investigating CFET technology. IBM’s differentiator is the staggered second layer combined with monolithic fabrication, building the second layer directly on the first rather than bonding independently fabricated pieces together, as AMD does with 3D V-Cache.
The approach faces significant challenges. Because the chip has two active layers, a defect in either layer renders the entire chip unusable, putting pressure on manufacturing yields. Thermal management is also critical: building the second layer must stay below 400 degrees Celsius (approximately 750 degrees Fahrenheit) to avoid melting the lower-layer connections. IBM has solved this but keeps its method proprietary.
IBM expects the technology to reach data centers within a decade. “I expect to have many conversations with designers about how they can use this technology,” said Huiming Bu, vice president of global semiconductor R&D at IBM.
Sources: IBM has unveiled chip technology that could help extend Moore’s Law another decade (MIT Technology Review, June 25, 2026)