For two decades, chips made from atomically thin materials such as molybdenum disulfide have promised to scale smaller and switch faster than silicon. But every attempt to shrink the gate stack, the transistor’s most important component, has come at a cost: the thinner the insulator, the more it scatters the charge carriers the transistor is supposed to move. A team at National Yang Ming Chiao Tung University (NYCU) and TSMC Corporate Research in Taiwan reports it has broken that tradeoff with a buffer layer just 0.42 nanometers thick, about the width of two atoms.
The work, published July 31 in Nature Electronics, demonstrates top-gate transistors on monolayer molybdenum disulfide (MoS2) with a transconductance of 0.45 millisiemens per micrometer at an equivalent oxide thickness of about 1 nanometer. Transconductance measures how strongly a change in gate voltage alters the current flowing through the device; it sets the voltage gain, switching speed, and bandwidth of the transistor. Getting a high value demands three things at once: a low equivalent oxide thickness (EOT), a scaled channel length, and preserved carrier mobility. In 2D transistors, those three factors have resisted simultaneous optimization.
The tradeoff at the heart of 2D transistors
To control an atomically thin channel, the gate insulator must be extremely thin, ideally below one nanometer of equivalent oxide thickness. Materials with high dielectric constants, the so-called high-k dielectrics, make this possible. But high-k oxides are polar, and their optical phonons couple to charges in the nearby channel, a scattering mechanism that degrades carrier mobility exactly when the insulator gets closest to the semiconductor. The result had been a choice: a well-controlled transistor with sluggish carriers, or a fast channel with a leaky, poorly controlled gate.
The Taiwanese team’s innovation is an intermediate layer grown epitaxially, in atomic registry with the MoS2 lattice. They evaporated an epitaxial aluminum film just 0.3 nanometers thick directly onto the monolayer in an ultrahigh vacuum chamber, then oxidized it in place under low pressure to form an aluminum oxide interfacial layer of about 0.42 nanometers. On top of that they deposited hafnium oxide by atomic layer deposition. The interfacial layer serves two roles: it provides a uniform, dangling-bond-free surface on which the high-k oxide can nucleate evenly, and it suppresses the dielectric-induced scattering that had previously degraded mobility.
The result is a gate stack with an EOT of 1.06 nanometers and a peak transconductance of 0.45 mS per micrometer at a gate length of roughly 100 nanometers, with subthreshold swings around 75 millivolts per decade and an on-current of 330 microamperes per micrometer at 1 volt. The devices survived a 400-degree-Celsius forming-gas anneal, a requirement for compatibility with back-end processing.
Why the material choice matters
Equally important is how the MoS2 was made. The channel was grown by chemical vapor deposition (CVD) on sapphire and transferred to the device substrate, a route that scales to wafers. Previous demonstrations of sub-nanometer EOT in 2D transistors, such as a 0.67-nanometer EOT achieved with antimony oxide in 2023, relied on exfoliated flakes, material peeled by hand from bulk crystals that is unsuitable for manufacturing. CVD growth is the industrially relevant path, and this is the first time sub-1.1-nanometer EOT, strong gate control, and preserved mobility have been combined on CVD-grown monolayer material.
The paper’s authors, led by Wen-Hao Chang and Tsung-En Lee at NYCU and Iuliana P. Radu at TSMC Corporate Research, frame the advance in terms of interfaces rather than materials. Chang said the real competition in 2D semiconductors would not be about materials alone but about interface engineering, since the atomic boundary between channel and insulator is where the decisive physics lives. TSMC’s involvement signals that the question is no longer purely academic; the foundry is a partner in the research, and the work aligns with a broader industry push, including a June 2026 announcement by imec, ASML, and TSMC on 300-millimeter integration of 2D transistors.
What remains unsolved
The paper is careful about its limits, and the gap between demonstration and production remains wide. The measured intrinsic mobility of about 27 square centimeters per volt-second is respectable but far below the 100-200 cm2/Vs achieved in exfoliated flakes; the claim is that mobility no longer degrades notably when the gate stack is added, not that it sets records. Transconductance at 0.45 mS per micrometer still trails silicon FinFETs by more than an order of magnitude. Device statistics come from a dozen or so transistors, not full wafers, and organic residues from the transfer process were acknowledged as a source of variability in threshold voltage and subthreshold swing.
Thermal stability has been demonstrated only to 400 degrees Celsius, while some fabrication steps run hotter. The approach has not yet been shown to work for p-type channels such as tungsten diselenide, which would be needed for complementary logic. And the 0.42-nanometer figure describes the interfacial alumina layer, not the full gate stack; the equivalent oxide thickness of the complete stack is about 1 nanometer.
Industry roadmaps still place 2D channels in commercial production around 2034, at the 0.7-nanometer node. What this paper does is remove one of the most stubborn obstacles on that path: the demonstration that an atomically thin, epitaxially matched buffer can give a CVD-grown 2D transistor a gate thin enough to control it and a channel fast enough to matter.
Sources
1. Yuan-Chun Su, Po-Sen Mao, et al., “High-transconductance molybdenum disulfide top-gate transistors using epitaxial interface engineering,” Nature Electronics (2026), published online July 31, 2026. DOI: 10.1038/s41928-026-01672-7.
2. ScienceDaily, “A 0.42-nanometer interface pushes transistors beyond silicon,” August 2026. https://www.sciencedaily.com/releases/2026/08/260808234943.htm
3. NYCU press release, “NSTC, NYCU, and TSMC Break Key Barrier in 2D Semiconductors,” August 11, 2026. https://www.nycu.edu.tw/nycu/en/app/news/view?module=headnews&id=552&serno=149da2b1-c125-4a91-a84f-1e21e369f762
4. EurekAlert!, “Engineering the atomic interface opens a new path for atomically thin transistors,” August 4, 2026. https://www.eurekalert.org/news-releases/1138925
5. XenoSpectrum technical analysis, “Epitaxial interface engineering MoS2 transistor,” August 9, 2026. https://xenospectrum.com/en/epitaxial-interface-engineering-mos2-transistor-nature-electronics/