Verification methodologies struggle to keep up with AI in chip design

The semiconductor industry is facing a new kind of bottleneck: verification methodologies that cannot keep pace with the AI tools being deployed to solve them.

In a detailed analysis from Semiconductor Engineering, industry leaders from Synopsys, Cadence, ChipAgents, Arteris, and other firms describe a landscape where AI is being deployed in every possible way to accelerate chip development, but without a proven playbook for how to integrate it safely into verification workflows.

“It is incredible how voracious the consumption of AI is,” said Bradley Geden of Synopsys. “At the executive level, everybody is nervous about missing out. If their competition is suddenly able to tape out a chip in 6 months versus 18 months, then they lose. There’s definitely an arms race to adopt AI.”

The productivity gains are real. William Wang of ChipAgents reported that early customer results show agentic workflows can turn a 150-person verification team into the equivalent output of a 400-person team. However, quality remains paramount, AI is not trusted to make final signoff decisions, and experienced engineers must audit every AI-generated result.

The skill implications split across experience levels. For junior engineers, AI lowers the entry barrier by handling tool setup and context, but they often lack the judgment to evaluate AI outputs. For senior engineers, AI acts as a force multiplier, one senior engineer can supervise multiple AI agents, generating test cases and test benches rapidly. As Hamid Shojaei of Cadence put it: “The coding part is going to be replaced sooner or later.”

The lack of standard methodology means every company is forging its own path. Debug remains the largest time sink, consuming over 40 percent of verification time, and training AI agents to understand company-specific ecosystems is essential for effective root-cause analysis.

Trust remains the central unresolved issue. As Andy Nightingale of Arteris noted, silicon does not tolerate ambiguity, even when AI occasionally does.

Sources: Verification Methodologies Struggle To Keep Up With AI (Semiconductor Engineering, June 25, 2026)

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