The semiconductor industry is undergoing a fundamental shift from monolithic chip designs to heterogeneous systems built from chiplets, pre-designed blocks assembled into sophisticated system-in-packages. But existing single-die design tools are insufficient for the task, according to a detailed methodology published by Siemens EDA.
“Heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed IP,” wrote Keith Felton of Siemens EDA.
The approach, known as system-level technology co-optimization (STCO), requires a complete rethinking of the design workflow. The first step is creating a 3D digital twin, a full-system model that aggregates design IP from multiple sources into a single authoritative representation. This drives creation of interfaces and bump arrays for chiplets, bridges, interposers, and substrates, and produces a single system connectivity netlist.
Industry standards including IEEE 3Dblox, OCP CDX, and JEDEC JEP30 Part Model are emerging to address the challenge of diverse data formats from different suppliers.
After constructing the digital twin, the focus shifts to pathfinding optimal floorplans. High-speed interfaces such as HBM and UCIe require close proximity via silicon bridges. Mechanical objects, stiffeners, seal rings, thermal interface materials, heat spreaders, affect placement and clearance. Siemens’ EDA tools use machine learning algorithms to concurrently optimise connectivity and bump assignments across hierarchy levels.
Early predictive analysis is critical, the methodology notes. Power delivery network prototyping catches DC-drop issues before they become expensive to fix. Vertical stacking impedes heat escape, making early thermal evaluation essential. Route resource planning combines bus signals into hierarchical connectivity bundles to avoid manual rip-up and retry cycles.
“Identifying significant DC-drop issues early is recommended, prioritising problem detection over sign-off accuracy to prevent costly changes,” Felton wrote.
The shift from monolithic to chiplet-based design is being driven by the economics of advanced semiconductor manufacturing. As mask costs for sub-3nm nodes soar, stitching together smaller chiplets using advanced packaging is often more cost-effective than building a single giant die. The approach also allows mixing different process nodes, compute chiplets at the most advanced node alongside I/O or memory chiplets at mature nodes.
The methodology is part of a four-part series on streamlining 3D-IC design, covering creation of the digital twin, floorplan pathfinding, finalization of the design scenario, and signoff for fabrication.
Sources: Realizing The Future Of 3D-IC Design (Semiconductor Engineering, June 25, 2026)