AMD has formally detailed its sixth-generation Epyc server processor family, codenamed Venice, built on TSMC’s N2 (2-nanometer) node. The flagship Epyc 9996 packs 256 Zen 6c dense cores and 512 threads in a single socket, making it the highest-core-count publicly disclosed server CPU as of July 2026.
The Venice family represents AMD’s most aggressive server push yet, spanning roughly 35 SKUs across four sub-platforms. At the top sits the 9996, a 256-core, 512-thread monster with 1,024 megabytes of L3 cache, a 2.55 GHz base clock boosting to 4.1 GHz, and a 600-watt thermal design power. AMD claims a 3.4-times throughput advantage over Intel’s Xeon 6980P in TPCx-AI benchmarks, and a 2.2-times throughput lead over Nvidia’s Vera CPU in SPECrate integer tests, both measured at the same 600-watt power envelope using the GNU 15.2 compiler.
The architecture marks a manufacturing transition from FinFET to gate-all-around nanosheet transistors, allowing the Venice compute chiplets to integrate approximately 203 billion transistors. AMD pairs 2-nanometer compute chiplets with 6-nanometer input-output dies, using 32 cores per CCD. Standard Zen 6 cores scale to 128 cores per socket, while a separate high-frequency variant reaches 96 cores at up to 5.0 GHz boost.
Memory bandwidth gets a substantial upgrade. The SP7 platform supports 16-channel MRDIMMs up to 12,800 MT/s or DDR5 RDIMMs at 8,000 MT/s, yielding 1.6 TB/s per socket, compared to 1.2 TB/s for Nvidia Vera and 576 GB/s for AMD’s own previous-generation Turin. PCIe 6.0 support delivers 128 lanes in single-socket configuration and 160 in dual-socket.
AMD’s wider Venice portfolio includes three additional tiers. The Venice-X line arriving later in 2026 adds 3D V-Cache, boosting L3 to 1,152 MB on 96-core chips with clocks up to 5.15 GHz. The SP8 platform, targeting 2027, scales from 8 to 128 cores on a narrower 8-channel memory bus. A separate Verano platform, also due in 2027, offers up to 72 LPDDR5X-powered cores as a dedicated AI host node.
In agentic AI workloads simulating five agent personas, AMD’s 9996 scored a geomean throughput of 4.45, 2.5 times Intel’s Xeon 6980P and 1.5 times AMD’s own Turin generation. Vector search benchmarks using FAISS on the sift1m dataset showed 751,453 queries per second, a 2.3-times improvement over Intel and 1.6 times over Turin.
AMD’s Ravi Kuppuswamy described the launch as a portfolio play rather than a single flagship: “It’s not just a single processor. It’s a family.” The message is clear, AMD is positioning Venice as a catch-all answer for cloud, enterprise, HPC, and the rapidly growing agentic AI workload segment, all while staying within the same 600-watt power ceiling as its predecessor.
Sources: AMD’s 256-core Epyc 9996 Venice claims up to 3.4x jump (Yahoo/Tom’s Hardware, July 2026); AMD launches 6th Gen EPYC Venice CPUs (Technetbook, July 2026)