MRAM and RRAM are set to coexist as nonvolatile memory winners

Flash memory is stuck at 28nm, unable to scale further, and as chipmakers push deeper into advanced nodes, a new generation of nonvolatile memory technologies is stepping in to fill the gap. The contenders, however, are not competing for a single crown. The emerging picture is one of coexistence: different memories for different jobs.

Semiconductor Engineering’s analysis of the nonvolatile memory landscape finds that MRAM (magnetoresistive RAM) and RRAM (resistive RAM) will likely dominate, each serving distinct use cases. Phase-change RAM (PCRAM), meanwhile, is being left behind.

MRAM is positioning itself as the high-speed, high-endurance option for persistent working memory, think automotive systems, space electronics, and edge AI. Its read speeds hover around 10 picoseconds, close to SRAM but with the advantage of nonvolatility. Everspin, the leading MRAM vendor, sees particular promise in edge AI: “We believe that MRAM is going to play a significant contribution in edge AI,” said Sean Dougherty of Everspin. The technology comes in several flavors, toggle MRAM (oldest, commercialized by Everspin), STT MRAM (current mainstream), and SOT MRAM (still years away from commercialization), each balancing speed, endurance, and bit-cell size differently.

RRAM, by contrast, targets cost-sensitive, general-purpose embedded applications. It requires no exotic materials or specialized tools, making it easier to integrate into standard CMOS processes. Infineon, working with TSMC, has demonstrated RRAM with retention exceeding 1,000 hours at 175 degrees Celsius (348 degrees Fahrenheit), endurance of 250,000 code changes, and 15.2-nanosecond read speeds. Its primary role is in IoT microcontrollers, PMIC configuration memory, and firmware storage.

“RRAM is commonly targeted for general-purpose embedded nonvolatile memory, such as firmware storage in IoT microcontrollers,” said Suhail Zain of UMC.

PCRAM, once a promising candidate, has stalled. No commercial embedded PCRAM offerings exist on finFET nodes, and Synopsys reports no customer demand for PCRAM compilers. “PCRAM is on the market in planar CMOS technologies. However, we don’t observe any activities to bring PCRAM to finFET nodes,” noted Robert Wiesner of Infineon.

The shift is driven by the practical realities of chip design. Flash memory (NOR type) requires increasingly complex integration below 28nm, with foundries like TSMC supporting MRAM and RRAM down to 6nm and 12nm respectively. Both technologies add only a few extra back-end-of-line masks, making them straightforward to integrate into existing Advanced CMOS flows.

Beyond MRAM and RRAM, two older technologies are seeing renewed interest. Ferroelectric RAM (FeRAM) offers extremely high endurance and low write power, no current is needed, only voltage across the ferroelectric capacitor. CEA-Leti recently demonstrated FeRAM at 22nm using hafnium zirconium oxide, a CMOS-compatible material deposited via atomic layer deposition, opening the door to scaling beyond the traditional 130nm limit. “If you want to write information constantly and have it stored in a nonvolatile way, FeRAM is very appealing,” said Laurent Grenouillet of CEA-Leti.

And a newcomer called UltraRAM, developed by startup Quinas, uses III-V compound semiconductor floating gates with quantum resonant tunneling through triple-barrier heterostructures. Quinas claims extrapolated retention of over 10,000 years, no degradation after 10 million cycles, and switching speeds competitive with DRAM at 20nm. The technology targets specialized, low-volume applications initially, with a broader DRAM-replacement vision expected around 2029.

For the foreseeable future, no single memory technology will replace both flash and DRAM. Instead, designers will mix and match, MRAM for working memory that must survive power loss, RRAM for embedded storage in low-power devices, and the established stalwarts (NAND, DRAM, SRAM) where they remain cost-effective.

Sources: “New Nonvolatile Memory Winners Emerge” (Semiconductor Engineering, July 16, 2026)

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