By Marie
For decades, the semiconductor industry’s playbook was simple: make transistors smaller, pack more onto a chip, and computing power increases. That playbook is running out of pages. Transistor sizes are approaching fundamental limits set by the atomic structure of silicon and the laws of quantum mechanics.
A team at the University of Illinois Urbana-Champaign has demonstrated an alternative approach that does not require shrinking individual components. Instead, they build upward.
Published in Nature in May 2026, the work by Lam, Yu, Cao and colleagues introduces a method for monolithic three-dimensional integration of silicon transistors, stacking multiple layers of circuits directly on top of each other on the same substrate, connected at the transistor level.
“If you look at the actual size of transistors, they’re not getting smaller,” said Qing Cao, the study’s lead author and a materials science professor at UIUC. “If we’re going to keep up the trend of increasing processing power, we have to start thinking beyond just squeezing more devices on a single surface.”
The heat barrier
The fundamental challenge to stacking silicon circuits vertically is heat. Conventional silicon transistor fabrication requires temperatures up to 1,000°C, hot enough to damage or melt the metal wiring in any underlying circuit layer. Previous attempts at 3D integration have used alternative materials that can be processed at lower temperatures: metal oxides, carbon nanotubes, or polycrystalline silicon. All of them suffer from inferior electrical performance compared with single-crystalline silicon.
The Illinois team solved this by making the silicon itself thin enough that it can be processed at much lower temperatures. They used ultrathin single-crystalline silicon nanomembranes, just 10 nanometers thick, roughly the size of a protein molecule, transferred onto the substrate using a roll-laminator process.
Because the membranes are so thin, they are mechanically flexible and conform to the underlying surface without the need for high-temperature bonding. The entire fabrication runs at or below 400°C, compatible with back-end-of-line processing, meaning the metal wiring in lower layers is not damaged when upper layers are built.
What they built
The team demonstrated a three-layer chip with 625 transistors per layer. While modest compared with the billions of transistors in a modern processor, the achievement is a proof of concept that the approach works at wafer scale (demonstrated on 8-inch wafers).
The key performance metrics are striking. The stacked silicon transistors achieve a current density above 650 microamps per micrometer, three to four times greater than chips built with alternative materials such as metal oxides or carbon nanotubes. Inter-tier registration accuracy is below 10 nanometers, meaning the layers align precisely enough for high-density vertical connections.
The team also demonstrated functioning logic gates, inverters, NAND, NOR, and SRAM memory cells, operating across three tiers. “Today it takes six transistors on a single plane to store one bit of information,” Cao said. “With this approach, you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”
The path forward
The performance of these transistors approaches that of front-end-of-line silicon MOSFETs, the standard building blocks of today’s chips, surpassing all previously reported back-end-of-line-compatible transistor technologies. The researchers believe many more layers could be added in future iterations.
The work addresses one of the semiconductor industry’s most pressing challenges. As transistor miniaturization slows, vertical integration is widely seen as the most viable path to continue increasing compute density, particularly for AI and other data-intensive workloads that benefit from shorter distances between processing and memory.
The transition from a 625-transistor proof of concept to the billions needed in commercial chips will require significant engineering. But the demonstration that single-crystalline silicon, the same material that powers every modern computer, can be stacked at low temperatures and high performance opens a path that does not require abandoning the industry’s most mature manufacturing infrastructure.
Sources:
1. Lam, B. et al. “Monolithic three-dimensional integration of silicon transistors.” Nature 654, 652–659 (2026). DOI: 10.1038/s41586-026-10496-6
2. McEachran, R. “New 3D silicon chip stacks circuits on top of each other to boost computing power.” Live Science (16 July 2026). https://www.livescience.com/technology/electronics/new-3d-silicon-chip-stacks-circuits-on-top-of-each-other-to-boost-computing-power