Intel patent reveals XBM memory architecture as potential HBM alternative

Intel has published a patent for a novel high-bandwidth memory design called XBM (Cross-Batch Memory) that aims to challenge HBM4’s dominance in AI accelerators and data center processors, using UCIe interconnects and back-end-of-line DRAM to sidestep the cost and complexity of traditional HBM packaging.

HBM has become the de facto memory standard for AI hardware, but tight supply controlled by Samsung, SK Hynix, and Micron has created a structural bottleneck. Intel’s patent, titled “Package architectures having vertically stacked dies for high capacity memory,” outlines a fundamentally different approach.

How XBM differs from HBM. Rather than stacking DRAM dies vertically beside a logic die on a silicon interposer, the HBM model, XBM uses ultra-high-bandwidth DRAM blocks connected to UCIe I/O blocks operating at up to 32 GT/s. The memory dies use 1T1C (one-transistor, one-capacitor) cells fabricated in the back-end-of-line metal layers rather than the traditional front-end silicon area. This backend DRAM approach is already being explored by partners including PSMC (Powerchip Semiconductor Manufacturing Corp.).

Each XBM memory die is designed for capacities between 0.5 GB and 5.0 GB, with I/O routed through a base die. The architecture uses built-in repair mechanisms and eliminates the costly silicon interposer required by HBM, replacing it with UCIe-based chiplet connectivity.

Timeline. XBM remains at the patent stage. Industry observers expect any commercial implementation to target a 2030 or later window, placing it in the same long-term category as other next-generation memory concepts aimed at future AI and high-performance computing platforms.

The patent follows Intel’s earlier work on ZAM technology, a non-TSV high-bandwidth memory path developed with SoftBank and SaiMemory, and the NGDB (Next-Generation DRAM Bridge) architecture Intel described previously. Together, these efforts signal Intel’s broader push to reduce dependency on the HBM duopoly and create an open memory ecosystem built around UCIe.

Source: Tom’s Hardware, SemiVision, Part of Style (patent analysis)

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