As the semiconductor industry prepares for the transition to High-NA EUV lithography, a less discussed factor is quietly reshaping design decisions: the cost and complexity of photomasks. While mask costs are not blocking leading-edge scaling, they are increasingly influencing which designs, nodes, and processes chipmakers choose.
A panel of lithography experts convened by Semiconductor Engineering examined how mask economics, already a significant operational expense at current EUV nodes, will become even more consequential with High-NA EUV. The panel included Aki Fujimura of D2S, Glen Scheid of Micron, Harry Levinson of HJL Lithography, Germain Fenger of Symopsys, and an additional industry veteran.
The mask cost equation depends heavily on what a chip is for. AI and GPU chips, which Fujimura noted are seeing an extraordinary surge in demand, can absorb the expense. Nvidia CEO Jensen Huang has cited US$1 trillion (approximately £790 billion) in GPU orders, a scale that makes a US$350 million (approximately £276 million) High-NA EUV scanner a justifiable investment.
“For the leading edge, it’s very clear that there is huge demand,” Fujimura said. “More investment in compute power is seen as a necessary cost.”
Below the leading edge, the picture is different. Many fabs operate profitably at 28 nanometres and older nodes, where mask costs are a fraction of what they are at 3 nm and below. For low-margin products, every extra mask set cuts directly into profitability.
How masks influence design
EUV lithography has already changed mask economics in one important way: it reduces mask counts. Where 193 nm immersion lithography required triple or quadruple patterning for critical layers, EUV can do single patterning, cutting the number of masks needed. Inverse lithography technology (ILT), which produces curvilinear mask shapes, can reduce total mask count further by enabling single patterning where multiple masks would otherwise be required.
Fenger noted that curvilinear masks will become only slightly more expensive than traditional Manhattan-geometry masks as multi-beam mask writers become common, making the trade-off increasingly attractive.
Micron’s Scheid said mask costs are “always on the table” during design reviews. They are rarely the sole reason to reject a design approach, but they influence decisions about which process node to use, how many layers to put on a single mask, and whether to design for mask reuse across multiple products.
High-NA challenges
High-NA EUV introduces a set of new mask-related problems. The reduced depth of focus at the higher numerical aperture requires thinner resists, which in turn drives demand for metal-oxide photoresists with higher etch selectivity. Lam Research’s Aether dry resist, which allows vertical tuning of resist properties, is one response to this challenge.
Stitching is an entirely new problem. At High-NA, the smaller field size means some critical layers will require two masks that must be precisely interlaced. No existing metrology tool can load two masks and create a single wafer image for defect qualification. As Fenger put it: “What happens if you have a defect in both masks? How do you qualify whether your repair worked properly?”
Mask three-dimensional effects become stronger at High-NA, requiring thinner absorbers and potentially new multilayer structures. But Levinson was optimistic, noting that Fraunhofer researcher Andreas Erdmann has shown these effects can be used advantageously rather than treated as a problem.
The sub-resolution assist feature problem
One specific challenge highlighted by Fujimura involves sub-resolution assist features (SRAFs), small patterns placed on masks to improve depth of focus. The physics of High-NA requires SRAFs approximately 15 nanometres on the mask scale. Current fast resists cannot reliably produce features at that size.
“If it’s 20 nm, no problem,” Fujimura said. “If it’s 15 nm, it’s at that boundary.” The limit is not the mask writer but the resist material.
The panel’s consensus was that the industry has always solved these problems before and will do so again. But the path to High-NA EUV involves more than simply buying a US$350 million scanner. The surrounding ecosystem of masks, resists, metrology, and inspection must evolve in parallel, and mask economics will shape which designs make the transition first.
Sources: Semiconductor Engineering (June 22)